Velocity saturation in the extrinsic device: a fundamental limit in HFET's

Abstract

We have carried out an experimental study revealing that velocity saturation (/spl upsi//sub sat/) occurring in both the extrinsic source and drain sets a fundamental limit on maximum drain current and useful gate swing in HFET's. Using AlGaAs/n/sup +/-InGaAs HFET's as a vehicle, we find that first g/sub m/ and eventually f/sub T/ decline at high currents in two stages. Initially, the approach of /spl upsi//sub sat/ in the extrinsic device causes the small-signal source and drain resistances (r/sub s/ and r/sub d/) to rise dramatically, primarily degrading g/sub m/. As the current increases further, the large-signal source and drain resistances (R/sub s/ and R/sub d/) grow significantly as well, pushing the intrinsic HFET toward the linear regime. Combined with the rapid rise of r/sub s/ and r/sub d/, the accompanying increase in gate-drain capacitance forces f/sub T/ to decline through a strongly enhanced Miller effect. We associate this two-fold mechanism with a new regime of HFET operation, which we call the parasitic-resistance blow-up regime.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>