Abstract
In most of the digital signal processing (DSP) applications the critical operations are the multiplication and accumulation. Real-time signal processing requires high speed and high throughput Multiplier-Accumulator (MAC) unit that consumes low power, which is always a key to achieve a high performance digital signal processing system. In this paper, design of MAC unit is proposed. The used inside the MAC unit is based on the Sutra Urdhva Tiryagbhyam (Vertically and Cross wise) which is one of the Sutras of Vedic mathematics. Vedic mathematics is mainly based on sixteen Sutras and was rediscovered in early twentieth century. In ancient India, this Sutra was traditionally used for decimal number multiplications within less time. The same concept is applied for multiplication of binary numbers to make it useful in the digital hardware. Here, the coding is done in VHDL and synthesis is done in Xilinx ISE series. The combinational delay obtained after synthesis is compared with the performance of the Modified Booth Wallace Multiplier and High speed Vedic multiplier presented by Ramesh Pushpangadam. Our proposed Vedic seems to have better performance.
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