Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing

Abstract

In this paper, split into Part I and II, the impact of variations on single-edge triggered flip-flops (FFs) is comparatively evaluated across a wide range of state-of-the-art topologies. The analysis explicitly considers fundamental sources of variations such as process/voltage/temperature (PVT), as well as the clock network (clock slope variations). For each topology, the variations of performance, robustness against hold violations, energy and leakage are statistically evaluated and compared. The impact of layout parasitics is explicitly included in the circuit design loop. The presented results provide well-defined guidelines for variation-aware selection of the flip-flop topologies, and estimates for early budgeting of variations before detailed circuit design. Also, the analysis enables a deeper understanding of the sensitivity to variations of existing topologies across a wide range of sizes and loads. In particular, this Part I introduces the methodology, the targeted flip-flop topologies and investigates the impact of process variations on flip-flop timing.