Hold Time Issues and Impact of Variations on Flip-Flop Topologies

Abstract

In this chapter, hold time issues and the impact of variations on SET FFs are discussed. In order to improve the chapter readability, results related to DET FFs are summarized in the Appendix due to their minor relevance with respect to SET FFs, as described in Chap. 5. The analysis explicitly considers fundamental sources of variations such as process/voltage/temperature (PVT) variations, as well as variations induced by the clock network (clock slope). For each FF topology, the variations of performance, robustness against hold violations, energy and leakage are statistically evaluated through Monte Carlo simulations and compared. The presented results and the comparison permit to gain a deeper understanding of the sensitivity of the existing topologies to variations. From a design perspective, the presented results provide guidelines for variation-aware selection of the FF topologies, and for early variations budgeting before detailed circuit design.