Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory

Abstract

Research on a word-line (WL) driving scheme is essential because the effect of WL parasitic resistance and capacitance ( RC ) is more severe for high-capacity NAND flash memories. The WL under-driving scheme (WLUDS) mitigates the effect of parasitic RC by reducing the coupling capacitance between WLs. However, WLUDS increases the cell threshold voltage ( $V_{\mathrm {th}}$ ) distribution because of parasitic RC variation, which causes an overshoot of the programming voltage ( $V_{\mathrm {PGM}}$ ). In this study, we propose the variation-tolerant WL under-driving scheme (VTWLUDS) to reduce the effect of parasitic RC variation and $V_{\mathrm {PGM}}$ overshoot through the use of a three-phase $V_{\mathrm {PGM}}$ control. We also introduce the fast-verify WL driving scheme (FVWLDS) to reduce the effect of parasitic RC variation in the verify operation. We verified VTWLUDS and FVWLDS by performing an HSPICE simulation with Samsung’s transistor model for a NAND peripheral circuit. The simulation results showed that VTWLUDS achieved a sufficient $V_{\mathrm {th}}$ shift during the programming operation regardless of the WL parasitic RC variation. By using VTWLUDS and FVWLDS, we achieved 1304 $\mu \text{s}$ of total programming time ( $T_{\mathrm {PROG}}$ ) for a 512-Gb planar-type NAND flash memory.