Abstract
A sensing circuit is described for a spin-transfer torque magnetic random access memory (STT-MRAM). The sensitivity to the variations of magnetic tunneling junction (MTJ) resistance and transistor parameters is reduced by employing the degenerated cross-coupled sensing circuit (DCCSC). The reference cell is also implemented to minimize the variation sensitivity and avoid any read disturbance. The proposed DCCSC and the reference cell are applied to a 64-kb STT-MRAM array. Simulation results with a 65-nm CMOS process parameter show that the sensing margin is larger than 500 mV, for both the parallel and antiparallel states, and the access time is 2 ns, and the energy per bit sensing is only 0.195 pJ, assuming that the variation of the MTJ resistance is +/−20% and tunneling magnetoresistance ratio is 100%.
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