Abstract
In this study, we investigate the variation of threshold voltage and ON-cell current caused by cell gate length fluctuation in silicon–oxide–nitride–oxide–silicon (SONOS) NAND flash memory with virtual source and drain (VSD). The fluctuation in cell gate length caused by process errors such as line edge roughness, etch slope variation, and lithography resolution-induced error affects threshold voltage and ON-cell current considerably. Our results show that three-dimensional (3D) structures have robust immunity to the cell gate length fluctuation effect. From the viewpoint of array design, threshold voltage and ON-cell current variation due to cell gate length fluctuation can be reasonably mitigated by enlarging the cell gate length in a word line (WL) pitch and reducing the body doping concentration. In addition, the tendency of the variation by technology node scaling and the comparison with the junctionless NAND flash memory structure are also investigated.
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