Variability Improvement by Interface Passivation and EOT Scaling of InGaAs Nanowire MOSFETs

Abstract

High performance InGaAs gate-all-around (GAA) nanowire MOSFETs with channel length (Lch) down to 20nm have been fabricated by integrating a higher-k LaAlO3-based gate stack with an equivalent oxide thickness of 1.2nm. It is found that inserting an ultrathin (0.5nm) Al2O3 interfacial layer between higher-k and InGaAs can significantly improve the interface quality and reduce device variation. As a result, a record low subthreshold swing of 63mV/dec has been demonstrated at sub-80nm Lch for the first time, making InGaAs GAA nanowire devices a strong candidate for future low-power transistors.