Abstract
This paper analyses standard 6T and 7T SRAM (static random access memory) cell in light of process, voltage and temperature (PVT) variations to verify their functionality and robustness. The 7T SRAM cell consumes higher hold power due to its extra cell area required for its functionality constraint. It shows 60% improvement in static noise margin (SNM), 71.4% improvement in read static noise margin (RSNM) and 50% improvement in write static noise margin (WSNM). The 6T cell outperforms 7T cell in terms of read access time (TRA) by 13.1%. The write access time (TWA) of 7T cell for writing "1" is 16.6 x longer than that of 6T cell. The 6T cell proves it robustness against PVT variations by exhibiting narrower spread in TRA (by 1.2 x) and Twa (by 3.4x). The 7T cell offers 65.6% saving in read power (RPWR) and 89% saving in write power (WPWR). The RPWR variability indicates that 6T ell is more robust against process variation by 3.9x. The 7T cell shows 1.3x wider write power (WPWR) variability indicating 6T cell's robustness against PVT variations. All the results are based on HSPICE simulation using 32 nm CMOS Berkeley Predictive Technology Model (BPTM).
Highlights
Due to aggressive scaling of device dimensions, random variations in process, supply voltage and temperature (PVT) poses major challenges to the future high performance circuits and system design [1,2,3]
The threshold voltage (Vt) mismatch between neighbouring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin (SNM) [7]
Static random access memory (SRAM) design requires balancing among various design criteria such as minimizing cell area using smaller transistor, maintaining read/write stability, minimizing power consumption by reducing power supply, minimizing read/write access time, minimizing leakage current, reducing bitline swing to reduce power consumption, improving soft error immunity, etc
Summary
Due to aggressive scaling of device dimensions, random variations in process, supply voltage and temperature (PVT) poses major challenges to the future high performance circuits and system design [1,2,3]. The microscopic variations in number and location of dopant atoms in the channel region of the device induce deviations in device characteristics [4,5,6] These fluctuations are more pronounced in minimum-geometry devices commonly used in area-constraint circuits such as SRAM cells [7]. Designers will require reevaluation and analysis of static noise margin in scaled technologies to ensure stability of SRAM cell. This paper investigates leakage power consumption and the impact of PVT variations on SRAM’s design metrics at 32 nm technology node. It presents analysis of SNM, TRA, TWA, RPWR, WPWR and their variations due to the impact of process parameters, voltage and temperature variations.
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