Abstract
This paper investigates the impact of the random ferroelectric-dielectric (FE-DE) phase distribution on the memory window (MW) of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) with the aid of TCAD atomistic simulations. Our study indicates that the DE path from source to drain is detrimental to the MW, and down-scaling the gate length substantially increases the probability of forming DE path and the variability in the MW. In addition, the MW variability for scaled FeFET devices can be mitigated by reducing the grain size, even under the same grain-to-channel area ratio. Besides, when down-scaling the insulator thickness to increase the MW, the increased MW variability due to the random FE-DE grains needs to be considered. Our study may provide insights for future scaling of FeFET NVMs.
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