Improved Energy Efficiency for Ferroelectric FET Non-Volatile Memory using Split-Gate Design

Abstract

In this work, we investigate the energy efficiency and memory window of split-gate ferroelectric FET (SG-FeFET) non-volatile memory (NVM) compared with the single gate ferroelectric FET (FeFET) NVM. A novel sequential write scheme is proposed to improve the read distinguishability (I R1 /I R0 ), memory window (MW), and energy efficiency of SG-FeFET NVM. Sufficient MW is essential to meet the retention and endurance requirements of ferroelectric oxide based NVM. The impact of gate length (L G ) on the MW and I R1 /I R0 of SG-FeFET and FeFET with MFMIS structure is analyzed. Our results show that with fixed MW, FeFET with longer L G (= 190 nm) requires 2.5 V write voltage (Vwrite); while FeFET with shorter L G (= 50 nm) decreases the Vwrite to 2 V. Our proposed SG-FeFET NVM (L G = 50 nm) with sequential write scheme can further reduce the Vwrite to 1.85 V, and improve the write energy by 21%. SG-FeFET NVM with improved energy efficiency is beneficial for hardware implementations of deep neural networks (DNNs) for low power AI and IoT applications.