Validation of TSV thermo-mechanical simulation by stress measurement

Abstract

Because of the large mismatch in coefficients of thermal expansion (CTE) between copper vias and the silicon substrate in through-silicon vias (TSVs), thermal stresses are induced. These stresses cause severe reliability issues, such as performance degradation of stress-sensitive devices, and interfacial delamination between TSVs and the silicon substrate. Finite element method (FEM) simulation is a useful tool for thermal stress analysis; however, developers and users are concerned about the range of accuracy of simulation models. Direct validation of the thermal simulation via stress measurement is extremely difficult. As non-destructive methods can measure the stresses only at the surface or several micrometers below, it is difficult to measure the internal stresses. Furthermore, any attempt to use an internal measurement location in the sample affects the stress situation. We propose a methodology to validate the simulation model with stress measurements using polarized Raman spectroscopy on cross-sections of TSV samples. The stress-free assumption at room temperature for simulation was compensated for using the measured residual stresses. An accurate comparison of stress data between experiment and simulation was achieved by considering the re-location of measurement points under thermal deformation. The agreement between simulation and experimental data for radial and axial thermal stresses validated the simulation model.The validated simulation model is useful for structural parametric analysis of TSV. The proposed methodology with stress measurement by polarized Raman spectroscopy and stress analysis by simulation can be used to study the radial and axial thermal stress of other devices.