Abstract
Presented is a system combining the validation of algorithmic and RT hardware models with test pattern generation for production test. The used validation techniques are based on simulations of test executions on the modeled hardware. Therefor the system includes tools automatically determining the quality of executed tests for validation and evaluating results of simulation runs. The test pattern generation is similar to Levendels and Menons technique /1/, however it intensively uses presupposed controllability and observability as for instance guaranteed by a scan path. It is integrated into the validation tools and thoroughly utilizes the data they produce. So this test pattern generation causes only neglectable additional costs. An experimental application of the system produced good results.
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