Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connections

Abstract

The paper reveals a completely new and original structure of a Test Pattern Generator (TPG) dedicated for detection of crosstalk faults that may happen to bus-type connections between individual cores of a System on a Chip (SoC). The TPG is designed to generate either the MAFM (Maximum Aggressor Fault Model) sequence of test vectors or the XMAFM (eXtended Maximum Aggressor Fault Model) one, which guarantees that all possible crosstalk faults of the capacitive nature that may occur between individual lines of a digital bus are detectable. The study presents the synthesizable and parameterized (scalable) model of the mentioned TPG developed in the VHDL language. The proposed TPG structures feature with high working frequency and good scalability in terms of both the hardware overhead and length of the output test sequence. In addition, the TPG structure enables easy integration of the solution with Design for Testability solutions, such as a scan path, a wrapper designed in compliance with the IEEE 1500 standard or with the Built-in Self-Test circuits that might be already implemented in IP cores embedded in a SoC. In such a case the area overhead of the proposed structure never exceeds several dozens of equivalent gates, which is a negligible amount.