Utilizing Dynamic Partial Reconfiguration to Reduce the Cost of FPGA Debugging

Abstract

Debugging of Field-Programmable Gate Arrays (FPGAs) is a difficult task due to the limited access to the internal signals of the design. Embedded logic analyzers enhance the signal observability for FPGAs. These analyzers are implemented on the FPGA resources and they use the embedded memory blocks as trace buffers, so a limited number of signals can be observed using these analyzers due to resources constraints. Changing the traced set of signals requires re-synthesis, placement and routing of the whole design. In this paper, we propose a new methodology for FPGA debugging to change dynamically the set of signals to be observed at runtime, and consequently minimize the time required for debugging. The proposed methodology utilizes the Dynamic Partial Reconfiguration (DPR) technique to dynamically switch between different sets of signals. DPR creates a reconfigurable module (RM) to route each set of signals to an embedded logic analyzer. We demonstrate the proposed approach using Xilinx FPGA tools, finding that changing the set of signals to be observed requires only few milli-seconds to re-program the reconfigurable region (RR). The area overhead of the proposed methodology is lower than other traditional methods of using multiplexers as the DPR allows the routing module to only use buffers to connect a set of signals to the embedded logic analyzer.