Utilization of thin as-deposited amorphous silicon gate/emitter layer in advanced CMOS/BiCMOS processes

Abstract

The use of a thin (<250-nm) as-deposited amorphous silicon gate/emitter layer is demonstrated in a submicrometer BiCMOS process that utilizes self-aligned cobalt silicide. The use of a thin polysilicon layer enhances the bipolar transistor high-frequency performance by allowing shallower and uniform emitter formation through reduction of the emitter anneal thermal budget. The salicide formation on the emitter, however, resulted in a degradation in the emitter efficiency for polysilicon thicknesses below 200 nm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>