<title>Identification of amorphous silicon residues in a low-power CMOS technology</title>

Abstract

A large variety of physical analysis techniques are used in the semiconductor industry to identify defects impacting yield or reliability. Identification of a defect often requires the combined use of several techniques to give a clear understanding of the defect nature. In the present study, several microscopy techniques (SEM, TEM, Analytical-TEM, AFM and FIB) have been intensively used to identify the origin of residues observed on the edge of large active areas in a low power CMOS technology. A KLA automatic inspection system has been used for locating and quantifying the defects. It has been shown that the defects are related to amorphous silicon residues whose origin is related to the gate deposition process. In the process, the polysilicon gate is deposited in two steps. A first thin amorphous silicon layer is deposited, through which the Vt implant is done, followed by the deposition of a thick polysilicon layer. Analysis of defaults showed that the residues are related to a non-uniform thin oxide layer located between the thick polysilicon layer and the underlying thin amorphous silicon, which halts the polysilicon gate etch. Thicker native oxide on amorphous silicon due to humidity or drying spots is the presumed source of the thin non-uniform oxide. Increasing the HF dip before the polysilicon deposition eliminated almost all residues. No negative effect on the oxide quality or other electrical parameter has been observed. Eliminating altogether the amorphous-Si gate deposition process is an even more robust solution.