Abstract

Power dissipation is expected to increase exponentially to 150-250 W per chip over the next decade. To manage this large heat output, it is necessary to minimize the thermal resistance between the chip and a heat dissipation unit that the device is attached to. It is therefore important to further improve the thermal performance of thermal interface materials (TIMs), which can be achieved through 1) improvement of the bulk thermal conductivity of TIMs; and/or 2) reduction of interfacial thermal resistances between the TIM and the device and/or TIM and the heat dissipation unit. The latter improvement may be obtained by enhanced physical properties of TIMs (e.g., viscosity or wetting ability) and/or surface modification of the heat dissipation unit or the inactive side of the device. Researchers have tried to take advantage of the high 1D thermal conductivities of graphite fibers, and more recently of carbon nanotubes (CNT), to reduce the thermal resistance between the chip and the heat dissipation unit. The efforts can be classified into three categories: 1) Forming pre-aligned graphite fiber or CNT films that have high bulk thermal conductivities in the heat transport direction, and applying such films as TIMs; 2) incorporating randomly oriented graphite fibers or CNT into silicone or epoxy matrices in the presence or absence of a second filler to improve bulk thermal conductivities, and applying the thus-formed blend as thermal greases, or adhesives or gels; and 3) growing CNT or graphite fibers from the heat sink/spreader surface and/or silicon backside and assembling them together with a TIM a to increase the bulk heat transport property and reduce the interfacial resistances, In this paper, we will present results for each of the three approaches, and discuss the challenges facing each one.

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