Utilization Aware Power Management in Reliable and Aggressive Chip Multi Processors

Abstract

With increasing transistor density on a single chip, processor design in the nanoscale era is hitting power and frequency walls. Due to these challenges, processors not only need to run fast, but remain cool and consume less energy. At this juncture where no further improvement in clock frequency is possible, data dependent latching through timing speculation provides a silver lining. In this paper, (a) we present a novel power level switching mechanism using reliable and aggressive designs that support overclocking. Using the proposed framework, we achieve 40 percent speed-up and also observe 75 percent energy-delay squared product (ED $^2$ ) savings relative to the base architecture. (b) showcase the loss of efficiency in current chip multiprocessor systems due to excess power supplied. We propose a utilization-aware task scheduling (UTS)—a power management scheme that increases energy efficiency of chip multiprocessors. (c) demonstrate that UTS along with aggressive timing speculation extracts ample performance from the system without loss of efficiency, and also without breaching power and thermal constraints. We demonstrate that UTS improves performance by 12 percent due to aggressive power level switching and over 50 percent in ED $^2$ savings in comparing to traditional power management techniques.