Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process Variations

Abstract

Exhaustive speed testing of all the cores under extreme inter and intra-die process variations in a large chip multi processor (CMP) is expensive in terms of test time and may not guarantee full CMP functionality due to lack of coverage of timing failures induced by second-order effects such as cross talk, power/ground bounce and speed-limiting design bugs that are not "caught" by relevant combinatorial design verification algorithms. The goal of this research is to develop a methodology that allows the "safe" speed of each core in a large CMP to be determined under the assumption that some speed defects and design bugs are likely to escape conventional delay testing procedures. Accordingly, baseline speeds using conventional tests are determined for each CMP core using a comparison based speed-tuning algorithm. To prevent "blue screens" from any test escapes, relevant applications are then run on the CMP in "fail-safe/redundant" mode to "top-up" speed-defect coverage. Over a period of time, using a concurrent tuning algorithm, the true "safe speeds' of all the cores are determined in O(log(Fp)) steps, independent of the size of the array, where Fp is the number of discrete clock speeds possible. Subsequently, each core is run "independently" at its highest "safe' clock speed achieving maximum possible CMP performance.