Using Multiple Models for Debugging VHDL Designs*

Abstract

Debugging is a time-consuming task especially for larger programs written by a group of people. In this paper we describe the use of multiple models for debuggingVHDL designs, and presents some practical results. The models are derived from a general value-based model representing different fault situations that should be handled by a debugger. We propose the use of a probability-based selection strategy for selecting the most appropriate model in a given situation. For example large programs should be debugged using a model only distinguishing concurrent VHDL statements and not sequential statements. As a result of multimodel reasoning in this domain we expect performance gains allowing to debug larger designs in a reasonable time, and more expressive diagnosis results.