Using Mixed Logic Synthesis Tools in Open-Source FPGA Design Framework

Abstract

In recent years, several open-source logic synthesis tools and design frameworks have emerged. However, there is limited research on the interactive combinations of these logic synthesis tools. To exploit the optimization capabilities of these tools, in this paper, we mixed three logic synthesis tools to construct a synthesis toolchain. The toolchain was integrated into an open-source FPGA design framework (OpenFPGA) to demonstrate the re-sults in the full design flow. We evaluate Yosys, ABC, and the in-house synthesis tool ALSO for comparison. According to experimental results over EPFL benchmark suites, the combination of these three tools results in an average improvement of 47% in critical path delay with 22% overhead in the logic block area.