Abstract
Theoretically, the surrounding gate SOI MOSFET presents the best possible control of gate region and consequently the best possible Electrostatic Integrity. Cynthia (circular-section) and Pillar (square-section) surrounding gate SOI MOSFETs are examples of this kind of structure. In this paper is performed a comparative study, by 3D numerical simulations, between Cynthia and Pillar surrounding gate SOI MOSFETs, focusing on analog integrated circuits applications, by studying the transconductance over drain current ratio behavior, regarding the same aspect ratio and bias conditions. Both, conventional and Graded-Channel technologies are regarded in this work. It is shown that Cynthia approach allows a voltage gain improvement of up to approximately 10% and 20% in comparison to Pillar surrounding gate SOI nMOSFET, when biased in weak and moderate inversion regimes, respectively.
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