Using Binary Decision Diagram for Test Generation of Power Supply Noise in Digital Circuits

Abstract

The scaling of circuit design technology to ultra deep submicron has increased the sensitivity of circuit technology to various noise mechanisms such as power supply noise and leakage current noise, etc. The propagation of noise can happen through various modes like the power supply and the substrate to a sensitive receptor. The power supply noise can reduce the actual voltage level reaching a device, results in the loss of signal integrity. The type of noise may also cause the degradation of switching speed, timing faults, or logic functional failures. In this paper, a new approach is presented for the test generation of power supply noise in digital circuits, the approach is based on the binary decision diagrams. The test vectors of power supply noise are generated by building and operating several binary decision diagrams, such as the binary decision diagrams respectively corresponding to the normal circuits and the circuits whose signal lines have been assigned special logic values. A lot of experimental results show that if there are test vectors for the power supply noise in a circuit, then the test vectors can be generated by the approach proposed in this paper.