Generation of test patterns for defect and noise in VLSI circuits using binary decision diagrams

Abstract

Binary decision diagram can be used to give canonical representation to logic functions and manipulate functions by simple and efficient graph algorithms. In this paper, the generation of test pattern based on binary decision diagrams is studied for stuck-at faults and crosstalk faults in digital circuits. The binary decision diagrams corresponding to the normal circuit and faulty circuit are built, respectively. A binary decision diagram is built by the XOR operation of the two binary decision diagrams, each input assignment that leads to the leaf node labeled 1 is a test vector of the faults. Besides, the binary decision diagram is very sensitive to the variable ordering, the variable ordering used can have a significant impact on the number of nodes. A chaotic genetic algorithms is presented in this paper, which is used to find a variable ordering that minimizes the size of a binary decision diagram to get the test vectors of the faults in digital circuits in the shortest possible test time. Experimental results obtained with a lot of digital circuits show that all the test vectors of a fault can be obtained using the method presented in this paper.