Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design

Abstract

This case study discusses how to use adaptive circuits in a big dual-core microprocessor to combat process variation. The large die size also makes it suffer more on-die process variation. To prevent continuous design updates or multiple design optimizations, designs incorporate adaptive techniques that achieve the highest performance possible. Although adaptive techniques are not new, having been implemented to some degree for generations (for example, self-calibrating I/O), they have taken significant new roles in many design aspects. As adaptive designs proliferate, increasing amounts of effort go into testing them. This article presented two types of adaptive systems: the silicon-optimizing active deskew system and the silicon-monitoring power measurement and cache latent-error detection system. However, these adaptive circuits are the tip of a growing iceberg. As variability increasingly affects designs, designers will likely use more adaptive circuits to achieve the highest performance and reliability possible. New scaling issues, such as erratic bits, will make these adaptations even more necessary to the design's fundamental operation. With increasing use of adaptive circuits, designers will need to develop new test techniques to ensure high part quality and reliability