Using a Peg with a Small Molecule Weight to Enhance Copper Bottom-up Filling Performance of through Silicon Via with a Deep and Wide Dimensions

Abstract

Three-dimensional (3D) chip stacking has been proposed for a long time, because “More than Moore” concept has been a possible solution to overcome the limitation of gate line width of a MOS. A deep and wide TSV could be superfilled with copper electroplating within 3 houses, by adding polyethylene glycol (PEG) with a small molecular weight, mainly due to its wetting capability. The dimensions of the TSV used in this work were 50 μm diameter and 245 μm depth. The TSVs used in this work had two types of seed layer. One was a traditional copper seed layer and the other was reduced graphene oxide (rGO) layer. Both TSVs were plated in a copper plating bath containing chloride and acidic copper sulfate as well as a suppressor, leveler and an accelerator. In addition, we added PEG with a small molecular weight. The filled TSVs were examined by cross-sectional analysis using an optical microscope (OM) and a scanning electron microscope (SEM). Keywords Through Silicon Via, Copper Electroplating, Reduced Graphene Oxide, 3D IC References [1] Wei-Ping Dow, Chih-Chan Li, Meng-Wen Lin, Ging-Wen Su, and Chen-Chia Huang “Copper Fill of Microvia Using a Thiol-Modified Cu Seed Layer and Various Levelers” Journal of The Electrochemical Society. 156(8) D314-D320 (2009).[2] Kondo, K, Akolkar, R.N, Barkey, D.P, Yokoi, M "Copper Electrodeposition for Nanofabrication of Electronics Devices, Chapter 2 Supression Effect and Additive Chemistry" Springer, Chemistry, Electrochemistry, Nanostructure Science and Technology (2014). Figure 1