Abstract

A novel analysis routine is proposed that visualizes the opening of a transistor channel using Electron Beam Induced Current (EBIC) with a net zero-volt bias across a channel. nFET devices on a 7 nm technology node chip were examined in two different regions of the sample. With varying gate voltage, the device turn-on was clearly evident in the resulting EBIC image. Quantitative analysis of the resulting currents is demonstrated, and shows the channel opening up at voltages earlier than shown by I-V measurement. A mechanism for this difference is proposed. The analysis, also involving a 2-dimensional map of the space, provides opportunities for detecting regional variations in the electrical properties or performance at the high resolutions afforded with a scanning electron microscope (SEM).

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