Abstract
We have successfully integrated 2 Mb arrays with SiO 2/Al 2O 3 stacks as inter-poly dielectric (IPD) fabricated in a proven 130 nm embedded Flash technology. Gate stack write/erase high voltages (HV) can be reduced by 3 V. Write/erase distributions show evidence of bit pinning which can be explained by barrier lowering along Al 2O 3 grain boundaries. Reliability assessment of the 2 Mb array reveals promising data retention and cycle endurance, indicating the absence of charge trapping in the high- k IPD. Despite several integration issues, these results demonstrate the high potential of Al 2O 3 IPDs in embedded Flash technologies.
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