Abstract
To maintain the excellent performance shown during the LHC's Run-1 the Level-1 Trigger of the Compact Muon Solenoid experiment underwent a significant upgrade. One part of this upgrade is the re-organization of the muon trigger path from a subsystem-centric view in which hits in the drift tubes (DT), the cathode strip chambers (CSC), and the resistive plate chambers (RPC) were treated separately in dedicated track-finding systems to one in which complementary detector systems for a given region (barrel, overlap, and endcap) are merged at the track-finding level. This fundamental restructuring of the muon trigger system required the development of a system to receive track candidates from the track-finding layer, remove potential duplicate tracks, and forward the best candidates to the global decision layer.An overview will be given of the new track-finder system for the barrel region, the Barrel Muon Track Finder (BMTF), as well as the cancel-out and sorting layer: the upgraded Global Muon Trigger (μGMT). Both the BMTF and μGMT have been implemented in a Xilinx Virtex-7 card utilizing the microTCA architecture. While the BMTF improves on the proven and well-tested algorithms used in the Drift Tube Track Finder during Run-1, the μGMT is an almost complete re-development due to the re-organization of the underlying systems from track-finders for a specific detector to regional track finders covering a given area of the whole detector. Additionally the μGMT calculates a muon's isolation using energy information received from the calorimeter trigger. This information is added to the muon objects forwarded to the global decision layer, the so-called Global Trigger.
Highlights
To maintain the excellent performance shown during the Large Hadron Collider (LHC)'s Run-1 the Level-1 Trigger of the Compact Muon Solenoid experiment underwent a significant upgrade
One part of this upgrade is the re-organization of the muon trigger path from a subsystem-centric view in which hits in the drift tubes (DT), the cathode strip chambers (CSC), and the resistive plate chambers (RPC) were treated separately in dedicated track-finding systems to one in which complementary detector systems for a given region are merged at the track-finding level
The barrel muon track-finder (BMTF) and μGMT are implemented in a Xilinx Virtex-7 690 Field-Programmable Gate-Arrays (FPGAs) placed on an Advanced Mezzanine Card (AMC), the Master Processor 7 (MP7), built by Imperial College [4], which provides a significant increase in resources compared to the chips used in the legacy system
Summary
The Level-1 Trigger of the Compact Muon Solenoid (CMS) experiment is responsible for reducing the event-rate from the nominal LHC bunch-crossing frequency of 40 MHz to 100 kHz. The general operating principle for the Level-1 Trigger is to find local features of physics objects in early stages of the trigger chain and successively combine these to regional physics objects. The general operating principle for the Level-1 Trigger is to find local features of physics objects in early stages of the trigger chain and successively combine these to regional physics objects They are subsequently received by a global stage where they are sorted before being sent to the Global Trigger (GT). The GT can trigger a read-out decision based on programmable algorithms. These algorithms work on full physics objects such as muons and jets and can include topological conditions
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