Evaluation of Data Transmission at 80MHz and 160MHz Over Backplane, Copper and Optical Links

Abstract

The bunch clock frequency of the LHC accelerator at CERN is specified as 40.07897 MHz [1]. Most of the LHC experiments will utilize this frequency, its multiples or derivatives as the main frequency of data transmission for their synchronous Trigger and DAQ electronic systems. For example, the triggering system of the Cathode Strip Chamber (CSC) sub-detector at the CMS experiment comprises the onchamber anode and cathode electronics, the off-chamber boards housed in 9U crates mounted on the periphery of the Endcap iron disks, and one Track Finder (TF) crate located in the underground counting room (Fig.1). Due to the significant amount of data from the front end, the trigger patterns are multiplexed and sent from the CSC chambers over copper cables using the LVDS standard at 80 MHz. For the same reason the data patterns transmitted over backplanes in the peripheral and TF crates are also multiplexed and sent at 80MHz using the GTLP standard. Optical links from the peripheral crates to the TF are operated at 80 MHz as well. Finally, the parallel LVDS links to the Global Muon Trigger (GMT) run at 40 MHz. Figure 1: CSC Trigger Electronic System A proposed Super LHS (SLHC) upgrade [2] would increase the operating frequency of the accelerator, and be challenging for many synchronous data transmission systems. The goal of this work was to evaluate possible solutions for data transmission at 80 MHz and 160 MHz suitable for the SLHC era. We have used an existing hardware designed for the CSC electronic system for evaluation of data transmission at 160 MHz using the LVDS and GTLP logical standards. We have designed a new evaluation board to study the optical links operating at 160 MHz. The results of measurements and possible solutions are presented. I. GTLP BACKPLANE INTERFACE Gunning Transceiver-Logic Plus (GTLP) is a widely used logical interface for point-to-point and bussed data transmission over backplane. Within the CSC electronic system it is used for the point-to-point transmission in the peripheral and TF crates at 80 MHz. The total number of data sources is 288 (9 boards) in the peripheral and 384 (12 boards) in the TF crate. The boards that receive all these signals reside in the middle of each crate (the Muon Port Card (MPC) [3] in the peripheral and the Muon Sorter (MS) [4] in the TF crate). Both backplanes also utilize a 40 MHz control GTLP bus. The TF backplane is a 6U, 21-slot multiplayer custom board residing in the 9U crate below the J1 part of the VME64x backplane. A pairs of Texas Instruments SN74GTLPH16912 transceivers are used in the TF crate and pairs of National Semiconductor GTLP16612 driver and Fairchild GTLP18T612 receiver are used in the peripheral crate. There are three parameters that may be adjusted to optimise the GTLP performance: termination resistance Rt, termination voltage Vt, and a reference voltage Vref for GTLP receivers. Termination resistors of 56 Ohm for all point-to-point GTLP lines are located on the receiver boards (MPC and MS) while the 100 Ohm terminations for a control bus are located on both ends of the custom backplane. The termination voltage is provided from a custom backplane and fixed at +1.5V. The reference voltage Vref can be adjusted (0.9V... 1.1V) with a potentiometer on a receiver board. We found that the best performance (duty cycle close to 50% and widest “safe window”) is achievable with the Vref=0.9V. In both backplanes the main master 40 MHz clock is distributed to all slots over individual LVDS lines of equal length from a common source, the Clock and Control Board (CCB) [5]. This board carries a mezzanine TTCrq card that is an interface to LHC Timing, Trigger and Control system [1]. All the peripheral and TF boards are based on various Xilinx FPGA devices. They produce internal 80 MHz clocks by doubling the master CCB clock. These 80 MHz clocks are well aligned on all trigger boards and are used to send data to the MPC and MS. After GTLP-to-LVTTL conversion on the MPC and MS boards an input data patterns are clocked in into the FPGA on adjustable 80 MHz clock produced by the DLL or DCM modules in the FPGA. The fine clock adjustments can be as low as 100..250 ps. We have chosen the MS board for evaluation purposes. The main Xilinx Virtex-2 FPGA on the MS receives as many as 384 80 MHz data bits, performs sorting “4 best tracks out of 36” and transmits the four best selected patterns to the