Abstract
This paper presents the design of a low-drift, curvature-corrected bandgap voltage reference (BGR) realized in a 0.35μm 3.3V triple-well CMOS technology having vertical NPN BJT transistors. The proposed circuit takes advantage of a block bulk isolation strategy improving the substrate noise sensitivity at the BGR output more than 100dB up to 100MHz. The simulated circuit achieves a mean temperature coefficient of 6.2ppm/°C over the temperature range of −40 to 125°C with 4.1ppm/°C standard deviation without any trimming. The circuit operates down to 2V and consumes 31.5μA from a single 3.3V supply. Its line regulation is less than 0.07% per Volt while its supply voltage changes from 2V to 3.6V. The power supply rejection (PSR) of the circuit is −76.5dB at 100Hz. The peak-to-peak output noise is 4.66μV integrated within the frequency range of 0.1–10Hz. The proposed circuit occupies an area of (515μm×320μm) 0.165mm2.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call