Abstract
In this work, a novel CMOS compatible process for Si-based materials has been presented to form SiGe nanowires (NWs) on SiGe On Insulator (SGOI) wafers with unprecedented thermoelectric (TE) power factor (PF). The TE properties of SiGe NWs were characterized in a back-gate configuration and a physical model was applied to explain the experimental data. The carrier transport in NWs was modified by biasing voltage to the gate at different temperatures. The PF of SiGe NWs was enhanced by a factor of >2 in comparison with bulk SiGe over the temperature range of 273 K to 450 K. This enhancement is mainly attributed to the energy filtering of carriers in SiGe NWs, which were introduced by imperfections and defects created during condensation process to form SiGe layer or in NWs during the processing of NWs.
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