Abstract
This paper report the technological routes used to build horizontal and vertical gate all-around (GAA) Field-Effect Transistors (FETs) using both Si and SiGe NanoWires (NWs). Horizontal Si and SiGe nanowires FETs are characterized in back gate configuration. Vertical devices using Si nanowires (NWs) show good characteristics with an I ON /I OFF ratio close to 106 and sub-threshold slope around 145 mV/decade. Finally, vertical SiGe devices also obtained with the same technological process present an I ON /I OFF ratio from 103 to 104 but also poor dynamics which can be explained by the high interface traps density.
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