Universal test set for detecting stuck-at and bridging faults in double fixed-polarity Reed–Muller programmable logic arrays

Abstract

A testable design for detecting stuck-at and bridging faults in programmable logic arrays (PLAs) based on double fixed-polarity Reed-Muller (DFPRM) expression is presented. DFPRM expression has the advantage of compactness and easy testability. The EXOR part in the proposed structure is designed as a tree of depth (/spl lceil/log/sub 2/ s/spl rceil/+1), where s is the number of product terms and sum terms in the given DFPRM expression realised by PLAs. This solves an open problem of designing an EXOR-tree-based RMC network that admits a universal test set. For an n-variable function, a test sequence of length (2n+8) vectors is sufficient to detect all single stuck-at and bridging faults in the proposed design. The proposed EXOR-tree-based network reduces circuit delay significantly compared with cascaded EXOR-based design. The test sequence is independent of the function and the circuit-under-test, and the test set can be stored in a ROM for built-in-self-test.