Unique capacitance phenomenon of a 100nm double-gate FD SOI NMOS device with n/sup +//p/sup +/ poly top/bottom gate

C.P Yang,J.B Kuo,C.H Hsu

doi:10.1109/icsict.2004.1434964

Unique capacitance phenomenon of a 100nm double-gate FD SOI NMOS device with n/sup +//p/sup +/ poly top/bottom gate

C.P Yang, J.B Kuo + Show 1 more

https://doi.org/10.1109/icsict.2004.1434964

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Publication Date: Jan 1, 2004

#Fully-depleted SOI NMOS #Double-gate Fully-depleted SOI + Show 8 more

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Abstract

This paper reports the unique capacitance phenomenon of 100nm double-gate (DG) fully-depleted (FD) SOI NMOS device with the n/sup +//p/sup +/ poly top/bottom gate. Based on the 2D simulation result, the gate-drain/source capacitance (C/sub GD//C/sub GS/) of the device shows a sudden fall at the gate voltage of 0.5V due to the existence of the hole accumulation/depletion in the bottom channel controlled by the p/sup +/ bottom gate.

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