Unified MOSFET scaling theory using the variational method

Abstract

Using the variational method, the two-dimensional Poisson equation is solved in the MOSFET device region including the gate oxide region, depletion region and buried oxide region (for a silicon-on-insulator [SOI] device). An analytical expression for the potential distribution together with a new natural gate length scale for the MOSFET is derived. The two-dimensional (2D) effects in front gate dielectric, back gate dielectric and silicon film can all be taken into account in this derivation. A comparison of the short channel effect for the uniform channel doping bulk MOSFET, intrinsic channel doping bulk MOSFET, SOI MOSFET and double-gated MOSFET is conducted using our model. The validity of electrical equivalent oxide thickness approximation is also investigated using this model. It is found that our model can be applied over a wide range of εI / ε0 with quite good accuracy. The results are verified by 2D numerical simulation using the 2D device simulator MEDICI.