Unified chip hardware architecture of KD-tree mean-based trainer and speeding-up classifier with repeat-point searching for various applications

Abstract

In this paper, we propose a total ASIC solution of unified low-latency K-dimensional tree (KD-tree) chip hardware architecture, including online mean-based trainer and speeding-up classifier. As compared with the other works in the current literature, we also develop a first KD-tree chip implementation to simultaneously perform training and classification tasks. Instead of supporting only one specific application, our work can be widely applied for various applications and well-verified with different datasets. Meanwhile, for different purposes, we also develop three useful design techniques, such as efficient trainer with mean-based splitting (ET-MBS), speeding-up classifier with repeat-point searching (SC-RPS), and double-leaf tree structure (DLTS). With TSMC 40-nm CMOS technology, the post-APR ASIC chip layout is well-verified with 7 representative datasets for various applications. The total core area only occupies 0.357 mm2, operating at a maximum frequency of 474 MHz and consuming power of 71.6 mW. Regarding online training, the worst-case training latency is only 1.9 μs for dealing with 1 K data. As for classification performance, the decision throughput varies from 0.51 GBps to 3.56 GBps.