UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS

Abstract

A new and improved Unified Clock and Power (UniCaP) architecture relies on dual-path feedback to further reduce supply-voltage (V dd ) margins in an ARM Cortex M0 processor while minimizing both peak cycle loss (Δϕ max ) and cycle-loss recovery time (T recovery ) associated with adaptive clocking. Measurements on a 65nm test chip demonstrate 91–99% V dd margin reduction and 38X T recovery improvement over [3]. We also report measurements that quantify the impact of clock distribution delay (τ dist ) and V dd sensitivity on V dd margin reduction.