A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains

Abstract

Correctly operating digital SoC domains at their target frequencies require the addition of supply voltage ( $V_{\mathrm{ dd}}$ ) guardbands to account for supply droop events and temperature variation. These guardbands degrade processor energy efficiency, especially in low-voltage sensor and IoT applications due to increased delay sensitivity to temperature and $V_{\mathrm{ dd}}$ variation. In this paper, we present an all-digital unified clock and power (UniCaP-SC) architecture that combines switched-capacitor (SC)-based voltage control and clock frequency regulation into a single loop to significantly reduce required $V_{\mathrm{ dd}}$ guardbands. A UniCaP-SC test chip consisting of a near-threshold voltage (NTV) ARM Cortex-M0 processor was fabricated in 65-nm CMOS. The fully integrated system enables all-digital construction, aggressive $V_{\mathrm{ dd}}$ margin reduction, and continuous $V_{\mathrm{ dd}}$ scalability using SC-based voltage converters while no additional decoupling capacitance (decap). Test-chip measurements demonstrate a 16% $V_{\mathrm{ dd}}$ reduction corresponding to a 94% $V_{\mathrm{ dd}}$ margin recovery or an equivalent $3.2\times $ increase in the operating clock frequency ( $f_{\mathrm{ clk}}$ ).