Understanding Hot Carrier Degradation and Variation in FinFET Technology

Abstract

In this paper, our recent studies on the hot carrier degradation (HCD) in FinFETs, as well as HCD-induced dynamic variability, are summarized. The kinetics and statistics of FinFET HCD are experimentally investigated. New observations on HCD are reported, which are due to the simultaneous generation of both interface and oxide traps. Based on the trap-based approach, instead of the conventional carrier-based approach, the HCD and its variations are well-described with the proposed multi trap-based compact models, that are unified over the full $\{V_{gs},V_{ds}\}$ bias region. The typical average locations of the HCD-induced traps in FinFET under the worst-case stress condition are also identified. The results are helpful for the physical understanding and modeling of HCD, and the reliability-aware circuit design for FinFET technology.