Underfill delamination analysis of flip chip on low-cost board

Abstract

Underfill delamination analysis of flip chip on low-cost board is presented in this study. The delamination propagation rates at the interface between chip and underfill have been measured by using C-SAM inspection of flip chip assemblies under thermal cycle loading. The experimental measurement was done in 4 cases, that were type B with fine solder joint and fractured solder joint, and type D with fine and fractured solder joint. In the finite element simulations related, the strain energy release rates G and the phase angles /spl phi/ near the delamination crack tip were calculated for 4 measurement cases by employing the fracture mechanical method. The Paris half-empirical equation was determined from the delamination propagation rates measured and the energy release rates simulated. The energy release rates G with different delamination crack length a were also simulated. The G/spl sim/a curve represents a convex shape when the crack propagates and indicates that the delamination crack may be stable and after propagating a certain length the crack will be arrested in flip chip assembly.