Abstract

This paper describes a ultra-wideband (UWB) three-stage cascaded high gain amplifier with low group delay variation for phased-array radar system. The shunt inductor at the input not only provides an electrostatic discharge (ESD) path to ground, but also introduces a new notch for S11, thus extending the matching bandwidth. Staggered tuning of load impedance peaks at each stage facilitates a balance between flat gain and low group delay variation. The output stage further enhances the overall gain while reinforcing bandwidth and stability through resistive feedback, and employs an adaptive bias circuit for linearity improvement. Implemented in SMIC 40-nm CMOS technology, the proposed amplifier achieves good input impedance matching, flat gain and low group delay variation of ±73.5 ps over 4.7–16 GHz. The whole power consumption is 198.3 mW and the output 1 dB compression point (OP1dB) is greater than 9 dBm. After careful design, the chip size is 0.64 mm2.

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