Ultra-thin strained-SOI CMOS for high temperature operation

Abstract

We have investigated mobility behaviors of ultra-thin strained-Si channel in fully-depleted (FD) strained-SOI CMOS at high temperature, which is a realistic chip operation condition. Although the decrease in the mobility enhancement with a decrease in strained-Si thickness determines the lower limit of strained-Si thickness, we have found that this lower limit becomes thinner at temperatures higher than room temperature. This is because the mobility degradation by the quantum-mechanical confinement (QMC) effect and MOS interface charges is relaxed at higher temperatures. This fact means that strained-SOI CMOS with thinner strained Si films, advantageous in terms of short channel effects, is acceptable under the real operation conditions.