Ultrashallow Junction Formation Using Novel Plasma Doping Technology beyond 50 nm MOS Devices

Abstract

In this paper, we demonstrate a novel plasma ion-shower doping (PLAD) technique for fabricating a nanoscale silicon-on-insulator metal-oxide-semiconductor field effect transistors (SOI MOSFETs). The source drain (S/D) extensions of the SOI n-MOSFETs were formed by elevated-temperature (ET) PLAD. Even though activation annealing after PLAD was excluded to minimize the diffusion of dopants, which resulted in laterally abrupt S/D junction, we obtained a low sheet resistance of 920 Ω/□ by the ET PLAD at 230°C. The fabricated SOI n-MOSFET with a gate length of 50 nm adopted in the proposed junction formation technique showed suppressed short-channel effects. The successful operation of a MOSFET with a high-κ gate dielectric and metal gate revealed that the proposed junction formation technique is compatible with devices made of low-thermal-budget material.