ULTRARAM: Toward the Development of a III–V Semiconductor, Nonvolatile, Random Access Memory

D Lane,M Hayne,P D Hodgson,R Beanland,R J Potter

doi:10.1109/ted.2021.3064788

D Lane, M Hayne + Show 3 more

Open Access

https://doi.org/10.1109/ted.2021.3064788

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Abstract

ULTRARAM is a III-V compound semiconductor memory concept that exploits quantum resonant tunneling to achieve nonvolatility at extremely low switching energy per unit area. Prototype devices are fabricated in a 2×2 memory array formation on GaAs substrates. The devices show 0/1 state contrast from program/erase (P/E) cycles with 2.5 V pulses of 500- μs duration, a remarkable switching speed for a 20 μm gate length. Memory retention is tested for 8×10 4 s, whereby the 0/1 states show adequate contrast throughout, whilst performing 8×10 4 readout operations. Further reliability is demonstrated via program-read-erase-read endurance cycling for $10^{6}$ cycles with 0/1 contrast. A half-voltage array architecture proposed in our previous work is experimentally realized, with an outstandingly small disturb rate over 10 5 half-voltage cycles.

Highlights

A ‘‘universal memory” should combine the best aspects of dynamic random access memory (DRAM) and flash.In essence, it must have very robust logic states that can, be changed
In ULTRARAM electrons are transported into and out of the floating gate (FG) via triple-barrier resonant tunneling (TBRT) structure formed from InAs/AlSb heterojunctions [4]
This layer provides the necessary band offsets with InAs to block all carrier flow through the control gate (CG) [9] but requires the memory tunneling structure to be reversed such that tunneling for P/E cycles occurs from the source of the cell (Fig. 1)

Summary

INTRODUCTION

A ‘‘universal memory” should combine the best aspects of dynamic random access memory (DRAM) and flash. In ULTRARAM electrons are transported into and out of the FG via triple-barrier resonant tunneling (TBRT) structure formed from InAs/AlSb heterojunctions [4] This resolves the paradox of universal memory, as the tunneling structure provides a high-energy barrier when there is no bias applied, but allows resonanttunneling (i.e., transparent barriers) at program/erase (P/E) voltages of around 2.5 V, approximately ten times lower than flash. The design is amended to include an Al2O3 gate dielectric formed via atomic layer deposition (ALD) This layer provides the necessary band offsets with InAs to block all carrier flow through the CG [9] but requires the memory tunneling structure to be reversed such that tunneling for P/E cycles occurs from the source of the cell (Fig. 1)

FABRICATION

CONCLUSION