Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing

Abstract

Balancing the PMOS/NMOS strength ratio is a key issue to maximize the noise margin, and hence, functional yield of CMOS logic gates in the subthreshold region. In this work, the PMOS/NMOS strength ratio was balanced using a poly-biasing technique in conjunction with back-gate biasing provided in a 28 nm fully depleted silicon on insulator (FDSOI) technology. A 32-bit adder based on minority-3 (min-3) gates and a 16-bit adder based on Boolean gates have been implemented. Chip measurement results show highly energy efficient adders, so that the 32-bit and 16-bit adders achieved minimum energy point (MEP) of 21.5 fJ at 300 mV and 12.62 fJ at 250 mV, respectively. In comparison to adders reported in other works in the same technology, the energy per 1-bit addition of the 32-bit adder is improved by 35% and for the 16-bit adder this improvement in energy consumption is 23%. The designed adders were functional down to a supply voltage of 110 mV. Additionally, the minimum V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> of the 32-bit adder decreased to 79 mV by applying a reverse back bias voltage to the PMOS devices.