Design of high speed and low power full adder in sub-threshold region

Abstract

To solve the serious problem of threshold loss that causes non-full-swing at the out-put of 1-bit full adder, an arrangement in which all the transistors are forced to operate in sub-threshold regime is proposed in this paper. But this will in turn bring additional area and delay overhead. In this work, full swing at the output of 1-bit full adder is retained with reduced area and delay overhead. An additional capacitor working in the differential voltage mode will be replacing the transistor that is used to reduce the threshold loss problem at the output of 9T based full adder as discussed in this paper. Previous works related to this domain concerns about reduction of power of only 1-bit adder. The work targets power and area reduction of 1/4/8/16 bit adders. Proposed adder shows maximum total power saving of 46.87 % and 25.99 % with respect to 8T and 9T adder configurations respectively.