Ultra-Low Quiescent Power Consumption LDO Regulators

Abstract

This chapter discusses challenges introduced by ultra-low power consumption in power management circuits. First of all, some techniques proposed in the literature to design ultra-low-power LDO regulators are reviewed. Then, an IC-LDO regulator with a quiescent current consumption lower than 600 nA is proposed. It is based on the classical LDO topology, which has been modified to include a class AB buffer between the output of the error amplifier and the gate of M\(_\mathrm{PASS}\). This way, a fast charge/discharge of its parasitic capacitance is achieved with the inherent low quiescent power consumption of class AB circuits. The proposed regulator has been fabricated in a standard 0.18 \(\upmu \)m CMOS technology. Experimental results show that the proposed regulator has a Figure of Merit in the state of the art.