Ultra-low power two-stage class-AB recycling double folded cascode OTA

Abstract

This paper presents an ultra-low power two-stage class-AB recycling double folded cascode (RDFC) fully differential operational transconductance amplifier (OTA) with high DC gain, unity gain frequency, slew rate, and common-mode rejection ratio (CMRR). Design and simulation of the proposed OTA is done in a 0.18-μm standard CMOS technology with a 1 V supply voltage. In this design, all transistors operate in weak inversion. A new RDFC structure with two separate paths to increase the gain and reduce the power consumption is used in the first stage of the proposed OTA. In the second stage, a class-AB amplifier is employed to improve the CMRR, DC gain and slew rate. Also, an output current control unit is included in the first stage to reduce power consumption. The use of the same proper bias circuit for the output current control unit and Miller resistor transistors establishes robust design against the process, voltage, and temperature (PVT) variations and reduces the power consumption. Post-layout simulation results of the proposed OTA demonstrate that it has a good performance over the previous state of the arts with DC gain of 136.8 dB, power consumption of 205.8 nW, and unity gain frequency of 141.7 kHz for a capacitive load of 2 × 7.5 pF.